Any conventional distribution network introduces skew (delay) due to finite signal propagation speed. For example, high frequency clock distribution in VLSI chips suffers from large delays produced mainly by charging/discharging parasitic line capacitances. These delays can be a substantial fraction of the clock period or even exceed it in severe cases. Even in the case of propagation at light speed, i.e. via on chip electrical transmission lines or silicon optical waveguides, the skew can easily accumulate to unacceptable levels for typical VLSI distances: approximately 12 ps for each mm. Likewise, in the case of transmission systems over multiple chips, PCBs, or subsystems, the skews can be extremely large.
The following considerations will focus on VLSI clock distribution, but similar arguments are valid for other cases of signal synchronization. In order to clock VLSI digital blocks that are spaced far apart with respect to each other, the relative skews must be first corrected, usually using Delay-Locked-Loop (DLL) of Phase-Locked-Loop (PLL) techniques. However, these brute force methods are becoming increasingly costly and power hungry with each new IC technology node, as the number of local clocking regions and the clock speed are increasing. Developing simpler and more efficient methods for skew elimination is highly desirable.